Due to the advantages of small size, reduced number of passive elements and lower cost, digital voltage converters have been popularly adopted. FIG. 1 shows a conventional digital boost converter 100, in which an output stage 102 converts an input voltage Vi to an output voltage Vo, an error amplifier 112 generates an error signal VE based on the output voltage Vo and a reference voltage Vref, an analog to digital converter 110 quantifies the error signal VE to generate a digital error signal VD, a digital compensator 108 generates a duty-ratio d by compensating the digital error signal VD, and a digital pulse width modulator 106 generates a pulse width modulation signal PWM based on the duty-ratio d for a driver 104 in the output stage 102 to switch a power switch M1. The duty-ratio d is defined asd=Ton/(Ton+Toff),  [EQ-1]where Ton and Toff are on-time and off-time, respectively, of the pulse width modulation signal PWM.
FIG. 2 shows a conventional digital buck-boost converter 200, in which an output stage 202 converts an input voltage Vi to an output voltage Vo, an error amplifier 212 generates an error signal VE based on the output voltage Vo and a reference voltage Vref, an analog to digital converter 210 quantifies the error signal VE to generate a digital error signal VD, a digital compensator 208 generates a duty-ratio d based on the digital error signal VD by compensating the digital error signal VD, and a digital pulse width modulator 206 generates a pulse width modulation signal PWM based on the duty-ratio for a driver 204 in the output stage 202 to switch switches M1 and M2. The duty-ratio d is also defined as the equation EQ-1, and the switches M1 and M2 are turned on and off at the same time. More details of digital voltage converters may refer to D. Maksimovic, R. Zane and R. Erickson, “Impact of Digital Control in Power Electronics,” Proceeding of 2004 International Symposium on Power Semiconductor Devices & Ics, pp. 13-22, and R. W. Erickon and D. Maksimovic, “Fundamentals of Power Electronics”, Kluwer Academic Publishers, 2001.
In steady state, the output voltage Vo and the duty-ratio d of the digital buck-boost converter 100 have the relationVo=Vi/(1−d),  [EQ-2]and the output voltage Vo and the duty-ratio d of the digital buck-boost converter 200 have the relationVo=d×Vi/(1−d).  [EQ-3]As shown in the equations EQ-2 and EQ-3, neither the converter 100 nor the converter 200 has a linear relation between the output voltage Vo and the duty-ratio d. In further detail, FIG. 3 shows the relations between the voltage conversion ratio Vo/Vi and the duty-ratio d, in which curve 300 represents the relation for the converter 100, and curve 302 represents the relation for the converter 200. As shown in the curves 300 and 302, as the duty-ratio d increases, the voltage conversion ratio Vo/Vi also increases in a non-linear manner. Since the conventional digital pulse width modulators 106 and 206 are implemented with digital control, their duty-ratio d is quantified. The quantization step Δd is also referred as resolution. In a conventional digital pulse width modulator, the quantization step Δd is constant. When it operates with high duty-ratio d (i.e. close to 1), the voltage conversion ratio Vo/Vi varies significantly when the duty-ratio d increases or decreases, thereby causing a great ripple at the output Vo. For example, if the converter 200 has a quantization step Δd of 0.01, then at the duty-ratio of 0.9, as shown by the curve 302, when the duty-ratio d increases or decreases by 0.01, the voltage conversion ratio Vo/Vi will change to 10 or 8 accordingly, thereby generating a ripple of ±1V on the output voltage Vo.
The resolution of the duty-ratio d in the converters 100 and 200 is determined by the digital pulse width modulators 106 and 206, respectively. In a conventional counter-based digital constant-frequency pulse width modulator, the timing resolution Tclk, bit width n and switching period Tsw are correlated, where the timing resolution Tclk is the clock cycle of the controllers 102 and 202, the bit width n is the bit number in each cycle of the pulse width modulation signal PWM, and the switching period Tsw is the switch cycle of the switch M1. Since the pulse width modulator operates at constant frequency, the switching period Tsw has a constant value. The timing resolution Tclk, bit width n and switch period Tsw have the relationTsw=2n×Tclk.  [EQ-4]To increase the resolution of the duty-ratio d, conventionally, the timing resolution Tclk is reduced, namely the clock frequency of the controllers 102 and 202 (1/Tclk) is increased. However, it is limited by this way. When the clock frequency (1/Tclk) of the controllers 102 and 202 reaches the order of GHz, the power loss will be too large to implement. Moreover, the smaller the timing resolution Tclk is, the more the implementation cost is.
Therefore, it is desired a digital boost and buck-boost converter capable of reducing the output ripple when operating with high duty-ratio.